View EN29GL128HH70BAIP_4864704.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 1 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 features ? single power supply operation - full voltage range: 2.7 to 3.6 volts read and write operations ? high performance - access times as fast as 70 ns ? v io input/output 1.65 to 3.6 volts - all input levels (address , control, and dq input levels) and outputs are determined by voltage on v io input. v io range is 1.65 to v cc ? 8-word/16-byte page read buffer ? 32-word/64-byte write buffer reduces overall programming time for multiple-word updates ? secured silicon sector region - 128-word/256-byte sector for permanent, secure identification - can be programmed and locked by the customer ? uniform 64kword/128kbyte sector architecture one hundred twenty-eight sectors ? suspend and resume commands for program and erase operations ? write operation status bits indicate program and erase operation completion ? support for cfi (common flash interface) ? persistent methods of advanced sector protection ? wp#/acc input - accelerates programming time (when v hh is applied) for greater throughput during system production - protects first or last sector regardless of sector protection settings ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completion ? minimum 100k program/erase endurance cycles. ? package options - 56-pin tsop - 64-ball 11mm x 13mm bga ? industrial temperature range. general description the en29gl128 offers a fast page access time of 25 ns with a corresponding random access time as fast as 70 ns. it features a write buffer that allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. this makes the device ideal for today?s embedded applications that require higher density, better performance and lower power consumption. en29gl128 128 megabit (16384k x 8-bit / 8192k x 16-bit) flash memory page mode flash memory, cmos 3.0 volt-only
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 2 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 connection diagrams figure 1. 56-pin standard tsop (top view) note: rfu= reserved for future use 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 rfu a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 rfu rfu rfu rfu a16 byte# vss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# vss ce# a0 rfu v io 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 3 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 figure 2. 64-ball ball grid array (top view, balls facing down) note: rfu= reserved for future use e8 vss d8 v io f8 rfu c8 rfu g8 rfu h8 rfu b8 a 22 a8 rfu a7 a 13 b7 a 12 c7 a 14 d7 a 15 h7 vss e7 a 16 f7 byte# g7 dq15 / a -1 a1 rfu b1 rfu c1 rfu d1 rfu e1 rfu f1 v io g1 rfu h1 rfu a2 a 3 b2 a 4 c2 a 2 d2 a 1 e2 a 0 f2 ce# g2 oe# h2 vss a3 a 7 b3 a 17 c3 a 6 d3 a 5 e3 dq0 f3 dq8 g3 dq9 h3 dq1 a4 ry / by# b4 wp# / acc c4 a 18 d4 a 20 e4 dq2 f4 dq10 g4 dq11 h4 dq3 a6 a 9 b6 a 8 c6 a 10 d6 a 11 e6 dq7 f6 dq14 g6 dq13 h6 dq6 a5 we# b5 reset# c5 a 21 d5 a 19 e5 dq5 f5 dq12 h5 dq4 g5 vcc
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 4 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 table 1. pin description figure 3. logic diagram pin name function a22?a0 a22?a0 dq0-dq14 data input/output. dq15 / a-1 dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# chip enable oe# output enable reset# hardware reset pin ry/by# ready/busy output we# write enable vcc supply voltage (2.7-3.6v) vss ground v io v i/o input. byte# byte/word mode selection wp#/acc write protect / acceleration pin ( wp# has an internal pull-up; when unconnected, wp# is at v ih .) rfu reserved for future use. not connected to anything e n2 9gl 128 dq0 ? dq15 (a-1) a 0 ? a 2 2 we # ce # ry/b y # rese t # byt e # oe# wp #/acc v io
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 5 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 table 2. product selector guide product number en29gl128 speed option full voltage range: vcc=2.7 ? 3.6 v v io =1.65 ? 3.6 v -70 max access time, ns (t acc ) 70 max page read access, ns(t pacc ) 25 max ce# access, ns (t ce ) 70 max oe# access, ns (t oe ) 25 block diagram we# ce# oe # state co ntr ol comman d register erase voltage generator input/output buffers program voltage generator ch ip ena ble out p ut enable logic data latch y-decode r x-decode r y-gating cell matrix timer vcc detector a 0 -a 2 2 vcc vss dq 0-d q15 (a-1) address latch bloc k pr otect switch es stb stb ry/by# v io
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 6 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 product overview en29gl128 is 128 mb, 3.0-volt-only, page mode flash devices optimized for today?s embedded designs that demand a large storage array and rich functionality. this product offers uniform 64 kword (128 kb) uniform sectors and feature v i/o control, allowing control and i/o signals to operate from 1.65 v to v cc . additional features include: ? single word programming or a 32-word buffer for an increased programming speed ? program suspend/resume and erase suspend/resume ? advanced sector protection methods for protecting sectors as required ? 128 words/256 bytes of secured silicon area for st oring customer secured information. the secured silicon sector is one time programmable.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 7 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 table 3. sector / persistent protection sector group address tables ppb group a22-a18 sector sector size (kbytes / kwords) address range (h) word mode (x16) ppb 0 sa0 128/64 000000?00ffff ppb 1 sa1 128/64 010000?01ffff ppb 2 sa2 128/64 020000?02ffff ppb 3 00000 sa3 128/64 030000?03ffff sa4 128/64 040000?04ffff sa5 128/64 050000?05ffff sa6 128/64 060000?06ffff ppb 4 00001 sa7 128/64 070000?07ffff sa8 128/64 080000?08ffff sa9 128/64 090000?09ffff sa10 128/64 0a0000?0affff ppb 5 00010 sa11 128/64 0b0000?0bffff sa12 128/64 0c0000?0cffff sa13 128/64 0d0000?0dffff sa14 128/64 0e0000?0effff ppb 6 00011 sa15 128/64 0f0000?0fffff sa16 128/64 100000?10ffff sa17 128/64 110000?11ffff sa18 128/64 120000?12ffff ppb 7 00100 sa19 128/64 130000?13ffff sa20 128/64 140000?14ffff sa21 128/64 150000?15ffff sa22 128/64 160000?16ffff ppb 8 00101 sa23 128/64 170000?17ffff sa24 128/64 180000?18ffff sa25 128/64 190000?19ffff sa26 128/64 1a0000?1affff ppb 9 00110 sa27 128/64 1b0000?1bffff sa28 128/64 1c0000?1cffff sa29 128/64 1d0000?1dffff sa30 128/64 1e0000?1effff ppb 10 00111 sa31 128/64 1f0000?1fffff sa32 128/64 200000?20ffff sa33 128/64 210000?21ffff sa34 128/64 220000?22ffff ppb 11 01000 sa35 128/64 230000?23ffff sa36 128/64 240000?24ffff sa37 128/64 250000?25ffff sa38 128/64 260000?26ffff ppb 12 01001 sa39 128/64 270000?27ffff ppb 13 01010 sa40 128/64 280000?28ffff
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 8 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 sa41 128/64 290000?29ffff sa42 128/64 2a0000?2affff sa43 128/64 2b0000?2bffff sa44 128/64 2c0000?2cffff sa45 128/64 2d0000?2dffff sa46 128/64 2e0000?2effff ppb 14 01011 sa47 128/64 2f0000?2fffff sa48 128/64 300000?30ffff sa49 128/64 310000?31ffff sa50 128/64 320000?32ffff ppb 15 01100 sa51 128/64 330000?33ffff sa52 128/64 340000?34ffff sa53 128/64 350000?35ffff sa54 128/64 360000?36ffff ppb 16 01101 sa55 128/64 370000?37ffff sa56 128/64 380000?38ffff sa57 128/64 390000?39ffff sa58 128/64 3a0000?3affff ppb 17 01110 sa59 128/64 3b0000?3bffff sa60 128/64 3c0000?3cffff sa61 128/64 3d0000?3dffff sa62 128/64 3e0000?3effff ppb 18 01111 sa63 128/64 3f0000?3fffff sa64 128/64 400000?40ffff sa65 128/64 410000?41ffff sa66 128/64 420000?42ffff ppb 19 10000 sa67 128/64 430000?43ffff sa68 128/64 440000?44ffff sa69 128/64 450000?45ffff sa70 128/64 460000?46ffff ppb 20 10001 sa71 128/64 470000?47ffff sa72 128/64 480000?48ffff sa73 128/64 490000?49ffff sa74 128/64 4a0000?4affff ppb 21 10010 sa75 128/64 4b0000?4bffff sa76 128/64 4c0000?4cffff sa77 128/64 4d0000?4dffff sa78 128/64 4e0000?4effff ppb 22 10011 sa79 128/64 4f0000?4fffff sa80 128/64 500000?50ffff sa81 128/64 510000?51ffff sa82 128/64 520000?52ffff ppb 23 10100 sa83 128/64 530000?53ffff
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 9 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 sa84 128/64 540000?54ffff sa85 128/64 550000?55ffff sa86 128/64 560000?56ffff ppb 24 10101 sa87 128/64 570000?57ffff sa88 128/64 580000?58ffff sa89 128/64 590000?59ffff sa90 128/64 5a0000?5affff ppb 25 10110 sa91 128/64 5b0000?5bffff sa92 128/64 5c0000?5cffff sa93 128/64 5d0000?5dffff sa94 128/64 5e0000?5effff ppb 26 10111 sa95 128/64 5f0000?5fffff sa96 128/64 600000?60ffff sa97 128/64 610000?61ffff sa98 128/64 620000?62ffff ppb 27 11000 sa99 128/64 630000?63ffff sa100 128/64 640000?64ffff sa101 128/64 650000?65ffff sa102 128/64 660000?66ffff ppb 28 11001 sa103 128/64 670000?67ffff sa104 128/64 680000?68ffff sa105 128/64 690000?69ffff sa106 128/64 6a0000?6affff ppb 29 11010 sa107 128/64 6b0000?6bffff sa108 128/64 6c0000?6cffff sa109 128/64 6d0000?6dffff sa110 128/64 6e0000?6effff ppb 30 11011 sa111 128/64 6f0000?6fffff sa112 128/64 700000?70ffff sa113 128/64 710000?71ffff sa114 128/64 720000?72ffff ppb 31 11100 sa115 128/64 730000?73ffff sa116 128/64 740000?74ffff sa117 128/64 750000?75ffff sa118 128/64 760000?76ffff ppb 32 11101 sa119 128/64 770000?77ffff sa120 128/64 780000?78ffff sa121 128/64 790000?79ffff sa122 128/64 7a0000?7affff ppb 33 11110 sa123 128/64 7b0000?7bffff ppb 34 sa124 128/64 7c0000?7cffff ppb 35 sa125 128/64 7d0000?7dffff ppb 36 sa126 128/64 7e0000?7effff ppb 37 11111 sa127 128/64 7f0000?7fffff
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 10 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 table 4. device operating modes 128m flash user mode table dq8-dq15 operation ce# oe# we# reset# wp#/acc a0- a22 dq0- dq7 byte# = v b ih b byte# = v b il b read l l h h l/h a b in b d b out b d b out b write l h l h (note 1) a b in b d b in b d b in b accelerated program l h l h v b hh a b in b d b in b d b in b dq8- dq14= high-z, dq15 = a -1 cmos standby v b cc b 0.3v x x v cc 0.3v h x high-z high-z high-z output disable l h h h l/h x high-z high-z high-z hardware reset x x x l l/h x high-z high-z high-z notes: 1. addresses are a22:a0 in word mode; a22:a-1 in byte mode. 2. if wp# = vil, on the outermost sector remains protected. if wp# = vih, the outermost sector is unprotected. wp# has an internal pull-up; when unconnected, wp# is at vih. all sectors are unprotected when shipped from the factory (the secured silicon sector can be factory protected depending on version ordered.) 3. din or dout as required by command sequence, data polling, or sector protect algorithm. legend l = logic low = vil, h = logic high = vih, vhh = 8.5?9.5v, x = don?t care, ain = address in, din = data in, dout = data out
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 11 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 user mode definitions word / byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at logic ?1?, the device is in word configuration, dq0-dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq0-dq7 are active and controlled by ce# and oe#. the data i/o pins dq8-dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. v io control the v io allows the host system to set the voltage levels that the device generates and tolerates on all inputs and outputs (address, control, and dq signals). v io range is 1.65 to v cc . for example, a v io of 1.65-3.6 volts allows for i/o at the 1.65 or 3.6 volt levels, driving and receiving signals to and from other 1.65 or 3.6 v devices on the same data bus. read all memories require access time to output array data. in a read operation, data is read from one memory location at a time. addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive with the address on its inputs. the device defaults to reading array data after device power-up or hardware reset. to read data from the memory array, the system must first assert a valid address on a22-a0, while driving oe# and ce# to vil. we# must remain at vih. all addresses are latched on the falli ng edge of ce#. data will appear on dq15-dq0 after address access time (tacc), which is equal to the delay from stable addresses to valid output data.the oe# signal must be driven to vil. data is output on dq15-dq0 pins after the access time (toe) has elapsed from the falling edge of oe#, assuming the tacc access time has been meet. page read mode the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 8 words/16 bytes. the appropriate page is selected by the higher address bits a22-a3. address bits a2-a0 in word mode (a2 to a-1 in byte mode) determine the specific word within a page. the microprocessor supplies the specific word location. the random or initial page access is equal to tacc or tce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tpacc. when ce# is deasserted and reasserted for a subsequent access, the access time is tacc or tce. fast page mode accesses are obtained by keeping the ?read-page addresses? constant and changing the ?intra-read page? addresses. autoselect the autoselect mode provides manufacturer id, device identification, and sector protection information, through identifier codes output from the internal register (separate from the memory array) on dq7- dq0. the device only support to use autoselect command to access autoselect codes. it does not support to apply vid on address pin a9.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 12 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 ? the autoselect command sequence may be written to an address within a sector that is either in the read or erase-suspend-read mode. ? the autoselect command may not be written while the device is actively programming or erasing. ? the system must write the reset command to return to the read mode (or erase-suspend-read mode if the sector was previously in erase suspend). ? when verifying sector protection, the sector address must appear on the appropriate highest order address bits. the remaining address bits are don't care and then read the corresponding identifier code on dq15-dq0. program/erase operations these devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. during a write operation, the system must drive ce# and we# to vil and oe# to vih when providing address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. note the following: ? when the embedded program algorithm is complete, the device returns to the read mode. ? the system can determine the status of the program operation by reading the dq status bits. refer to the write operation status on page 22 for information on these status bits. ? an ?0? cannot be progra mmed back to a ?1.? a succeeding re ad shows that the data is still ?0.? ? only erase operations can convert a ?0? to a ?1.? ? any commands written to the device during the embedded program/erase are ignored except the suspend commands. ? secured silicon sector, autoselect, and cfi functi ons are unavailable when a program operation is in progress. ? a hardware reset and/or power removal immediately terminates the program/erase operation and the program/erase command sequence should be reinitiated once the device has returned to the read mode to ensure data integrity. ? programming is allowed in any sequence an d across sector boundaries for single word programming operation. ? programming to the same word address multiple times without intervening erases is permitted. single word programming single word programming mode is one method of programming the flash. in this mode, four flash command write cycles are used to program an individual flash address. the data for this programming operation could be 8 or 16-bits wide. while the single word pr ogramming method is supported by most devices, in gene ral single word programming is not recommended for devices that support write buffer programming. when the embedded program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by reading the dq status bits. ? during programming, any command (except the suspend program command) is ignored. ? the secured silicon sector, autoselect, and cfi functions are unava ilable when a program operation is in progress. ? a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. ? programming to the same address multiple times continuously (for example, ?walking? a bit within a word) is permitted.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 13 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 figure 4. single word program
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 14 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 write buffer programming write buffer programming allows the system to write a maximum of 32 words in one programming operation. this results in a faster effective word programming time than the standard ?word? programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which programming occurs. at this point, the system writes the number of ?word locations minus 1? that are loaded into the page buffer at the sector address in which programming occurs. this tells the device how many write buffer addresses are loaded with data and therefore when to expect the ?program buffer to flash? confirm command. the number of locations to program cannot exceed the size of the write buffer or the operation aborts. (number loaded = the number of locations to program minus 1. for example, if the system programs 6 address locations, then 05h should be written to the device.) the system then writes the starting address/data combination. this starting address is the first address/data pair to be programmed, and selects the ?write-buffer-page? address. all subsequent address/data pairs must fall within the elected-write-buffer-page. the ?write-buffer-page? is selected by using the addresses a22?a5. the ?write-buffer-page? addresses must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed across multiple ?write-buffer- pages.? this also means that write buffer programming cannot be performed across multiple sectors. if the system attempts to load programming data outside of the selected ?write-buffer-page?, the operation aborts.) after writing the starting address/data pair, the system then writes the remaining address/data pairs into the write buffer. note that if a write buffer address location is loaded multiple times, the ?address/data pair? counter is decremented for every data load operation. also, the last data loaded at a location before the ?program buffer to flash? confirm command is the data programmed into the device. it is the software's responsibility to comprehend ramifi cations of loading a write-buffer location more than once. the counter decrements for each data load operation, not for each unique write-buffer-address location. once the specified number of write buffer locations have been loaded, the system must then write the ?program buffer to flash? command at the sector address. any other address/data write combinations abort the write buffer programming operation. the write operation status bits should be used while monitoring the last address location loaded into the write buffer. this eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then check the write operation status at that same address. dq7, dq6, dq5, dq2, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer ?embedded? programming operation can be suspended using the standard suspend/resume commands. upon successful completion of the write buffer programming operation, the device returns to read mode. the write buffer programming sequence is aborted under any of the following conditions: ? load a value that is greater than the page buffer size during the ?number of locations to program? step. ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different write-buffer-page than the one selected by the ?starting address? during the ?write buffer data loading? stage of the operation. ? writing anything other than the program to buffer flash command after the specified number of ?data load? cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the ?last address location loaded?), dq6 = toggle, dq5 = 0. this indicates that the write buffer programming operation was aborted. note that the secured silicon sector, autoselect, and cfi functions are unavailable when a program
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 15 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 operation is in progress. write buffer programming is allowed in any sequence of memory (or address) locations. these flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. use of the write buffer is strongly recommended for programming when multiple words are to be programmed. figure 5. write buffer programming operation
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 16 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 sector erase sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. once the sector erase operation has begun, only the sector erase suspend command is valid. all other commands are ignored. if there are several sectors to be erased, sector erase command sequences must be issued for each sector. that is, only a sector address can be specified for each sector erase command . users must issue another sector erase command for the next sector to be erased after the previous one is completed. when the embedded erase algorithm is completed, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to ?write operation status? for information on these status bits. flowchart 4 illustrates the algorithm for the erase operation. refe r to the erase/program operations tables in the ?ac characteristics? section for parameters, and to the sector erase operations timing diagram for timing waveforms. figure 6. sector erase operation start write erase command sequence data poll from system or toggle bit successfully completed erase done data =ffh? yes no
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 17 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 chip erase command sequence chip erase is a six-bus cycle operation as indicated by table 13. these commands invoke the embedded erase algorithm, which does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory to an all zero data pattern prior to electrical erase. after a successful chip erase, all locations of the chip contain ffffh. the system is not required to provide any controls or timings during these operations. when the embedded erase algorithm is complete, that sector returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6/dq2. refer to ?write operation status? for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that sector has returned to reading array data, to ensure the entire array is properly erased. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the sector address is required when writing this command. this command is valid only during the sector erase operation. the sector erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. addresses are don?t-cares when writing the sector erase suspend command. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. after the erase operation has been suspended, the device enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces status information on dq7-dq0. the system can use dq7, or dq6, and dq2 together, to determine if a sector is actively erasing or is erase-suspended. after an erase-suspended program operation is complete, the device returns to the erase-suspend- read mode. the system can determine the status of the program operation using write operation status bits, just as in the standard program operation. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to write buffer programming and the autoselect for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspended sector is required when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. program suspend/program resume commands the program suspend command allows the system to interrupt an embedded programming operation or a ?write to buffer? programming operation so that data can read from any non-suspended sector. when the program suspend command is written during a programming process, the device halts the programming operation within 15 s maximum (5 s typical) and updates the status bits. addresses are ?don't-cares? when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any nonsuspended sector. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not within a sector in erase suspend or program suspend. if a read is needed from th e secured silicon sector area, then user must use the proper command sequences to enter and exit this region.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 18 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 the system may also write the autoselect command sequence when the device is in program suspend mode. the device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to program suspend mode, and is ready for another valid operation. after the program resume command is written, the device reverts to programming. the system can determine the status of the program operation using the write operation status bits, just as in the standard program operation. the system must write the program resume command (address bits are ?don't care?) to exit the program suspend mode and continue the programming operation. further writes of the program resume command are ignored. another program suspend command can be written after the device has resumed programming. accelerated program accelerated single word programming and write buffer programming operations are enabled through the wp#/acc pin. this method is faster than the standard program command sequences. if the system asserts v hh on this input, the device automatically enters the accelerated program mode and uses the higher voltage on the input to reduce the time required for program operations. the system can then use the write buffer load command sequence provided by the accelerated program mode. note that if a ?write-to-buffer-abort reset? is required while in acce lerated program mode, the full 3-cycle reset command sequence must be used to reset the device. removing v hh from the acc input, upon completion of the embedded program operation, returns the device to normal operation. ? sectors must be unlocked p rior to raising wp#/acc to v hh . ? the wp#/acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. ? it is recommended that wp#/acc apply v hh after power-up sequence is completed. in addition, it is recommended that wp#/acc apply from v hh to vih/vil before powering down v cc / v io . write operation status the device provides several bits to determine the status of a program or erase operation. the following subsections describe the function of dq1, dq2, dq3, dq5, dq6, and dq7. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embe dded program or erase algorithm is in progress or completed, or whether th e device is in erase susp end. data# polling is valid after the rising edge of the final we# pulse in th e command sequ ence. note that the data# polling is valid only for the last word bein g programmed in the write-buffer-page during write buffer programming. reading data# pollin g status on any word other than the last word to be progra mmed in the write- buffer-page returns false status information. during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active, then that sector returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device en ters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 19 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. howe ver, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq6-dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq 7 has valid data, the data output s on dq6-dq0 may be still invalid. valid data on dq7-d00 appears on successive read cycles. figure 7. write operation status flowchart dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 20 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address that is being programmed or erased causes dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase 2suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7. if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is writte n, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. toggle bit i on dq6 requires either oe# or ce# to be de-asserted and reasserted to show the change in state. dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase- suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. reading toggle bits dq6/dq2 whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erases operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determin es that the toggle bit is still toggling, the system also should note whether the value of dq5 is high. if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. if it is still toggling, the device did not complete the operation su ccessfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. note when verifying the status of a write operation (embedded program/erase) of a memory sector, dq6 and dq2 toggle between high and low states in a series of consecutive and contiguous status read cycles. in order for this toggling behavior to be properly observed, the consecutive status bit reads must not be interleaved with read accesses to other memo ry sectors. if it is not possible to temporarily prevent reads to other memory sectors, then it is recommended to use the dq7 status bit as the alternative method of determining the active or inactive status of the write operation.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 21 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device does not output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0. only an erase operation can change a 0 back to a 1. under this condition, the device ignores the bit that was incorrectly instructed to be programmed from a 0 to a 1, while any other bits that were correctly requested to be changed from 1 to 0 are programmed. attempting to program a 0 to a 1 is masked during the programming operation. under valid dq5 conditions, the system must write the reset command to return to the read mode (or to the erase- suspend-read mode if a sector was previously in the erase-suspend-program mode). dq3: sector erase timeout state indicator after writing a sector erase command sequence, the output on dq3 can be checked to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) when sector erase starts, dq3 switches from ?0? to ?1?. this device does not support multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since it immediately shows as a ?1? after the first 30h command. future devices may support this feature. dq1: write to buffer abort dq1 indicates whether a write to buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the ?write to buffer abort reset? command sequence to return the device to reading array data. table 5. write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/by# embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 standard mode embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspended sector invalid (not allowed) 1 program suspend mode program suspend read non-program suspended sector data 1 erase suspended sector 1 no toggle 0 n/a toggle n/a 1 erase suspend read non-erase suspended sector data 0 erase suspend mode erase suspend program (embedded program) dq7# toggle 0 n/a n/a n/a 0 busy(note 3) dq7# toggle 0 n/a n/a 0 0 write to buffer abort(note 4) dq7# toggle 0 n/a n/a 1 0 notes 1. dq5 switches to 1 when an embedded program, embedded erase, or write-to-buffer operation has exceeded the maximum timing limits. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to 1 when the device has aborted the write-to-buffer operation writing commands/command sequences during a write operation, the system must drive ce# and we# to vil and oe# to vih when providing an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce#. an erase operation can erase one sector or the entire device. table 3 indicates the address space that each sector occupies. the device address
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 22 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 space is divided into uniform 64kw/128kb sectors. a sector address is the set of address bits required to uniquely select a sector. icc2 in ?dc characterist ics? represents the active current specification for the write mode. ?ac characteristics? contains timing specification tables and timing diagrams for write operations. ry/by# the ry/by# is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . this feature allows the host system to detect when data is ready to be read by simply monitoring the ry/by# pin, which is a dedicated output and controlled by ce# (not oe#). hardware reset the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of trp (reset# pulse width), the device immediately terminates any operation in progress, tristates all ou tputs, resets the configuration register, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. to ensure data integrity program/erase operations that were interrupted should be reinitiated once the device is ready to accept another command sequence. when reset# is held at vss, the device draws v cc reset current (icc5). if reset# is held at vil, but not at vss, the standby current is greater. reset# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the flash memory upon a system reset. software reset software reset is part of the command set that also returns the device to array read mode and must be used for the following conditions: 1. to exit autoselect mode 2. when dq5 goes high during write status operation that indicates program or erase cycle was not successfully completed 3. exit sector lock/unlock operation. 4. to return to erase-suspend-read mode if the device was previously in erase suspend mode. 5. after any aborted operations the following are additional points to consider when using the reset command: ? this command resets the sectors to the read and address bits are ignored. ? reset commands are ignored during program and erase operations. ? the reset command may be written between the cycles in a program command sequence before programming begins (prior to the third cycle). this resets the sector to which the system was writing to the read mode. ? if the program command sequence is written to a sector that is in the erase suspend mode, writing the reset command returns that sector to the erase-suspend-read mode. ? the reset command may be written during an autoselect command sequence. ? if a sector has entered the autoselect mode while in the erase suspend mode, writing the reset command returns that sector to the erase-suspend-read mode. ? if dq1 goes high during a write buffer programming operation, the system must write the ?write to buffer abort reset? command sequence to reset the device to reading array data. the standard reset command does not work during this condition.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 23 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 advanced sector protection/unprotection the advanced sector protection/unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. this section describes the various methods of protecting data stored in the memory array. an overview of these methods in shown in figure 8. figure 8. advanced sector protection/unprotection lock register the lock register consists of 4 bits. the secured silicon sector protection bit is dq0, persistent protection mode lock bit is dq1, persistent sector protection otp bit is dq3 and dyb lock boot bit is dq4. if dq0 is ?0?, it mean s that the customer secured silicon area is locked and if dq0 is ?1?, it means
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 24 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 that it is unlocked. when dq1 is set to ?0?, the device is used in the persistent protection mode. dq3 is programmed in the eon factory. when the device is programmed to disable all ppb erase command, dq3 outputs a ?0?, when the lock register bits are read. similarly, if the device is programmed to enable all ppb erase command, dq3 outputs a ?1? when the lock register bits are read. likewise the dq4 bit is also programmed in the eon factory. dq4 is the bit which indicates whether volatile sector protection bit (dyb) is protected or not after boot-up. when the device is programmed to set all volatile sector protection bit protected after power-up, dq4 outputs a ?0? when the lock register bits are read. similarly, when the device is programmed to set all volatile sector protection bit unprotected after power-up, dq4 outputs a ?1?. each of these bits in the lock register are non-volatile. dq15- dq5 are reserved and will be 1?s. table 6. lock register dq15-5 dq4 dq3 dq2 dq1 dq0 reserved dyb lock boot bit ppb one time programmable bit reserved persistent protection mode lock bit secured silicon sector protection bit (default = 1) 0 = protected all dyb after boot-up 1 = unprotected all dyb after boot-up (default = 1) 0 = all ppb erase command disabled 1 = all ppb erase command enabled (default = 1) (default = 1) 0 = persistent protection enabled (default = 0) 0 = protected 1 = unprotect (default = 1) notes: 1. after the lock register bits command set entry command sequence is written, reads and writes for all sector are disabled, while reads from other sectors are allowed until exiting this mode. 2. only dq0 could be change by lock register bits co mmand for user. others bits were set by factory. after selecting a sector protection method, each sector can operate in any of the following three states: 1. constantly locked: the selected sectors are protected and can not be reprogrammed unless ppb lock bit is cleared via hardware reset, or power cycle. 2. dynamically locked: the selected sectors are protected and can be altered via software commands. 3. unlocked: the sectors are unprotected and can be erased and/or programmed. persistent protection bits the persistent protection bits are unique and nonvolatile. for sector 0~3 and 124~127 have one ppb for each sectors and for sector 4~123 have one ppb every four sectors (refer to figure 8 and table 3. sector / persistent protection sector group address tables) and have the same endurances as the flash memory. preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring. notes 1. each ppb is individually programmed and all are erased in parallel. 2. while programming ppb for the four sectors and data polling on programming ppb address, array data can not be read from any sectors. 3. entry command disables reads and writes for all sectors selected. 4. reads within that sector return the ppb status for that sector. 5. all reads must be performed using the read mode. 6. the specific sector address are written at the same time as the program command. 7. if the ppb lock bit is set, the ppb program or erase command does not execute and times-out without programming or erasing the ppb. 8. there are no means for individually erasing a specific ppb and no specific sector address is required for this operation. 9. exit command must be issued after the execution which resets the device to read mode and re- enables reads and writes for all sectors. 10. the programming state of the ppb for given sectors can be verified by writing a ppb status read command to the device as described by the flow chart shown in figure 9. user only can use dq6 and ry/by# pin to detect programming status.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 25 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 figure 9. ppb program algorithm note: ba = base address
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 26 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 dynamic protection bits dynamic protection bits are volatile and unique for each sector and can be individually modified. dybs only control the protection scheme for unprotected sectors that have their ppbs cleared (erased to ?1?). by issuing the dyb set or clear command sequences, the dybs are set (programmed to ?0?) or cleared (erased to ?1?), thus placing each sector in the protected or unprotected state respectively. this feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. notes 1. the dybs can be set (programmed to ?0?) or cleared (erased to ?1?) as often as needed. when the parts are first shipped, the ppbs are cleared (erased to ?1?) and upon power up or reset, the dybs can be set or cleared depending upon the ordering option chosen. 2. if the option to clear the dybs after power up is chosen, (erased to ?1?), then the sectorsmay be modified depending upon the ppb state of that sector (see table 7). 3. the sectors would be in the protected state if the option to set the dybs after power up is chosen (programmed to ?0?). 4. it is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. 5. the dyb set or clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. however, if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be cleared by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again locks the ppbs, and the device operates normally again. 6. to achieve the best protection, it is recommended to execute the ppb lock bit set command early in the boot code and protect the boot code by holding wp#/acc = vil. note that the ppb and dyb bits have the same function when wp#/acc = vhh as they do when acc =vih. persistent protection bit lock bit the persistent protection bit lock bit is a global volatile bit for all sectors. when set (programmed to ?0?), it locks all ppbs and when cleared (erased to ?1?), allows the ppbs to be changed. there is only one ppb lock bit per device. notes 1. no software command sequence unlocks this bit, but only a hardware reset or a power-up clears this bit. 2. the ppb lock bit must be set (programmed to ?0?) only after all ppbs are configured to the desired settings.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 27 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 figure 10. lock register program algorithm advanced sector protection software examples table 7. sector protection schemes: dyb, ppb and ppb lock bit combinations
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 28 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 table 7 contains all possible combinations of the dyb, ppb, and ppb lock bit relating to the status of the sector. in summary, if the ppb lock bit is locked (set to ?0?), no changes to the ppbs are allowed. the ppb lock bit can only be unlocked (reset to ?1?) through a hardware reset or power cycle. see also figure 8 for an overview of the advanced sector protection feature. hardware data protection methods the device offers two main types of data protection at the sector level via hardware control: ? when wp#/acc is at vil, the either the highest or lowest sector is locked (device specific). there are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. the following subsections describes these methods: wp#/acc method the write protect feature provides a hardware method of protecting one outermost sector. this function is provided by the wp#/acc pin and overrides the previously discussed sector protection/unprotection method. if the system asserts vil on the wp#/acc pin, the device disables program and erase functions in the highest or lowest sector independently of whether the sector was protected or unprotected using the method described in advanced sector protection/unprotection on page 24. if the system asserts vih on the wp#/acc pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. the wp#/acc pin must be held stable during a command sequence execution. wp# has an internal pull-up; when unconnected, wp# is set at vih. note if wp#/acc is at vil when the device is in the standby mode, the maximum input load current is increased. low v cc write inhibit when vcc is less than vlko, the device does not accept any write cycles. this protects data during vcc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until vcc is greater than vlko. the system must provide the proper signals to the control inputs to prevent unintentional writes when vcc is greater than vlko. write pulse ?glitch protection? noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. power-up write inhibit if we# = ce# = reset# = vil and oe# = vih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 29 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 power conservation modes standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.3 v. the device requires standard access time (tce) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is co mpleted. icc4 in ?dc characteristics? represents the standby current specification automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for tacc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. hardware reset# input operation the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of trp, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. when reset# is held at vss 0.3 v, the device draws icc reset current (icc5). if reset# is held at vil but not within vss 0.3 v, the standby current is greater. reset# may be tied to the system reset circuitry and thus, a system reset would also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. output disable (oe#) when the oe# input is at vih, output from the device is disabled. the outputs are placed in the high impedance state. (with the exception of ry/by#.) secured silicon sector flash memory region the secured silicon sector provides an extra flash memory region. the secured silicon sector is 128 words in length and all secured s ilicon reads outside of the 128-wo rd address range returns invalid data. the secure d silicon sector indicator bit, dq7, (at autos elect address 03h) is used to indicate whether or not the secured silicon sector is locked when shipped from the factory. please note the following general conditions: ? on power-up, or following a hard ware reset, the device reverts to sending commands to the normal address space. ? reads outside of sector sa0 return memory array data. ? sector sa0 is remapped from memory array to secured silicon sector array. ? once the secured silicon sector entry command is issued, the secured silicon sector exit command must be issued to exit secured silicon sector mode. ? the secured silicon sector is not accessible when the device is ex ecuting an embedded program or embedded erase algorithm. ? when sector sa0 is suspe nded, if system enters secured silicon sector mode , the secured silicon sector region cannot be read. if the system suspends the flash in other sectors except sa0, secured silicon sector region can be read normally.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 30 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 ? the acc function is not available when the secured silicon sector is enabled. table 8. secured silicon sector addresses secured silicon sector address range 000000h-000007h reserve for factory 000008h-00007fh determined by customer customer lockable secured silicon sector the customer lockable sec ured silicon sector is always ship ped unprotected (dq0 set to ?1?), allowing customers to utilize that sector in any manner they choose. if the security feat ure is not required, the secured silicon sector can be treated as an additional flash memory space. please note the following: ? once the secured silicon sector ar ea is protected, the secured silicon sector indicator bit (dq0) is permanently set to ?0.? ? the secured silicon sector can be read any nu mber of times, but can be programmed and locked only once. the secured silicon sector lock must be used with caution as on ce locked, there is no procedure available for unlocking the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. ? the accelerated programming (acc) is not availa ble when the secured silic on sector is enabled. ? once the secured silicon sector is locked and verified, the system must write the exit secured silicon sector region command sequen ce which return the device to the memory array at sector 0. ? the address 0h~7h in secured silicon sector is reserved for factory. secured silicon sector entry/exit command sequences the system can access the secured silicon sector region by issuing the three-cycle enter secured silicon sector command sequence. the device continue s to access the secured silicon sector region until the system issues the four-cycle exit secured silicon sect or command sequence. the secured silicon sector entry command allows the following commands to be executed ? read customer and factory secured silicon areas ? program the customer secured silicon sector after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the addresses normally occupied by sector sa0 within the memory array. this mode of operation continues until the system issues the exit secured silicon sector command sequence, or until power is removed from the device. common flash interface (cfi) the common flash interface (cfi) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-independent, jedec id- independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 31 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 the system can read cfi information at the addresses given in tables 9~12.in word mode, the upper address bits (a7?msb) must be all zeros. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode and the system can read cfi data at the addresses given in tables 9~12. the system must write the reset command to return the device to the autoselect mode.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 32 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 table 9. cfi query identification string addresses (word mode) data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) table 10. system interface string addresses (word mode) data description 1bh 0027h vcc min (write/erase) dq7-dq4: volt, dq3-dq0: 100mv 1ch 0036h vcc max (write/erase) dq7-dq4: volt, dq3-dq0: 100mv 1dh 0000h vpp min voltage (00h = no vpp pin present) 1eh 0000h vpp max voltage (00h = no vpp pin present) 1fh 0003h typical timeout per single byte/word write 2 n s 20h 0004h typical timeout for min size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max timeout for byte/word write 2 n times typical 24h 0005h max timeout for buffer write 2 n times typical 25h 0004h max timeout per individual block erase 2 n times typical 26h 0000h max timeout for full chip erase 2 n times typical (00h = not supported) table 11. device geometry definition addresses (word mode) data description 27h 0018h device size = 2 n bytes. 2**24=16mb=128mb 28h 29h 0002h 0000h flash device interface description (refer to cfi publication 100); 01h = x16 only; 02h = x8/x16 2ah 2bh 0006h 0000h max number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0001h number of erase block regions within device 2dh 2eh 2fh 30h 007fh 0000h 0000h 0002h erase block region 1 information (refer to the cfi specification of cfi publication 100) 128 uniform sectors (7fh + 1) 31h 32h 33h 34h 0000h 0000h 0000h 0000h erase block region 3 information (refer to the cfi specification of cfi publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information (refer to the cfi specification of cfi publication 100)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 33 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification of cfi publication 100) table 12. primary vendor-specific extended query addresses (word mode) data description 40h 41h 42h 0050h 0052h 0049h query unique ascii string "pri" 43h 0031h major version number, ascii 44h 0034h minor version number, ascii 45h 000ch address sensitive unlock (bits 1-0) 00 = required, 01 = not required technology (bits 5-2) 0001 = 0.18um, 0010 = 0.13um, 0011 = 90nm 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = minimum number of sectors per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0003h sector protect/unprotect scheme 00h = high voltage sector protection 01h = high voltage + in-system sector protection 02h = hv + in-system + software command sector protection 03h = software command sector protection 4ah 0000h simultaneous operation 00 = not supported, x = number of sectors 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0085h minimum wp#/acc (acceleration) supply voltage 00 = not supported, dq7-dq4: volts, dq3=dq0: 100mv 4eh 0095h maximum wp#/acc (acceleration) supply voltage 00 = not supported, dq7-dq4: volts, dq3=dq0: 100mv 4fh 00xxh top/bottom boot sector flag 04 = uniform sectors bottom wp# protect 05 = uniform sectors top wp# protect 50h 0001h program suspend 00 = not supported, 01 = supported 52h 0008h secured s ilicon sector (customer otp area) size 2 n bytes 53h 000fh hardware reset low time-out during an embedded algorithm to read mode maximum 2 n ns 54h 0009h hardware reset low time-out not during an embedded algorithm to read mode maximum 2 n ns 55h 0005h erase suspend latency maximum 2 n s 56h 0005h program suspend latency maximum 2 n s 57h 0000h bank organization 00 = data at 4ah is zero, x = number of banks
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 34 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 table 13. en29gl128 command definitions bus cycles 1 p st p cycle 2 p nd p cycle 3 p rd p cycle 4 p th p cycle 5 p th p cycle 6 p th p cycle command sequence cycles addr data addr data addr data addr data addr data addr data read 1 ra rd reset 1 xxx f0 000 7f word 555 2aa 555 100 1c 000 7f manufacturer id byte 4 aaa aa 555 55 aaa 90 200 1c word 555 2aa 555 x01 227e x0e 2221 x0f 2201 device id byte 4 aaa aa 555 55 aaa 90 x02 7e x1c 21 x1e 01 00 word 555 2aa 555 (sa) x02 01 00 autoselect sector protect verify byte 4 aaa aa 555 55 aaa 90 (sa) x04 01 word 555 2aa 555 program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa write to buffer byte 6 aaa aa 555 55 sa 25 sa wc pa pd wbl pd word program buffer to flash byte 1 sa 29 word 555 2aa 555 write to buffer abort reset byte 3 aaa aa 555 55 aaa f0 word 555 2aa 555 555 2aa 555 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 word erase/program suspend byte 1 xxx b0 word erase/program resume byte 1 xxx 30 word 555 2aa 555 secured silicon sector entry byte 3 aaa aa 555 55 aaa 88 word 555 2aa 555 secured silicon sector exit byte 4 aaa aa 555 55 aaa 90 xx 00 word 55 cfi query byte 1 aa 98 accelerated program 2 xx a0 pa pd legend x = don?t care ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of the we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits amax?a16 uniquely select any sector. wbl = write buffer location. the address must be within the same write buffer page as pa. wc = word count is the number of write buffer locations to load minus 1 and maximum value is 31 for word and byte mode.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 35 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 table 14. en29gl128 command definitions bus cycles 1 p st p cycle 2 p nd p cycle 3 p rd p cycle 4 p th p cycle 5 p th p cycle 6 p th p cycle command sequence cycles addr data addr data addr data addr data addr data addr data word 3 555 aa 2aa 55 555 40 command set entry byte 3 aaa aa 55 55 aaa 40 program 2 xxx a0 xxx data read 1 00 rd lock register command set exit 2 xxx 90 xxx 00 word 3 555 aa 2aa 55 555 c0 ppb command set entry byte 3 aaa aa 55 55 aaa c0 ppb program 2 xxx a0 sa 00 all ppb erase 2 xxx 80 00 30 ppb status read 1 sa rd global non-volatile ppb command set exit 2 xxx 90 xxx 00 word 3 555 aa 2aa 55 555 50 ppb lock command set entry byte 3 aaa aa 555 55 aaa 50 ppb lock set 2 xxx a0 xxx 00 ppb lock status read 1 xxx rd global volatile freeze ppb lock command set exit 2 xxx 90 xxx 00 word 3 555 aa 2aa 55 555 e0 dyb command set entry byte 3 aaa aa 555 55 aaa e0 dyb set 2 xxx a0 sa 00 dyb clear 2 xxx a0 sa 01 dyb status read 1 sa rd volatile dyb command set exit 2 xxx 90 xxx 00 legend x = don?t care rd(0) = read data. sa = sector address. address bits amax?a16 uniquely select any sector. pwd = password pwdx = password word0, word1, word2, and word3. data = lock register contents: pd(0) = secured silicon sector protection bit, pd(1) = persistent protection mode lock bit, pd(2) = password protection mode lock bit.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 36 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 table 15. dc characteristics (t a = - 40c to 85c; v cc = 2.7-3.6v) notes: 1. byte# pin can also be gnd 0.3v. byte# and reset# pin input buffers are always enabled so that they draw power if not at full cmos supply voltages. 2. maximum i cc specifications are tested with vcc = vcc max. 3. not 100% tested. symbol parameter test conditions min typ max unit i li input leakage current 0v v in vcc 5 a i lo output leakage current 0v v out vcc 1 a 5mhz 15 30 ma i cc1 v cc active read current ce# = v il ; oe# = v ih ; v cc = v cc max 10mhz 25 45 ma i io2 v io non-active output ce# = v il , oe# = v ih 0.2 10 ma ce# = v il , oe# = v ih , v cc = v cc max, f = 10 mhz 1 10 i cc2 v cc intra-page read current ce# = v il , oe# = v ih , v cc = v cc max, f = 33 mhz 5 15 ma i cc3 v cc active erase/ program current ce# = v il , oe# = v ih , v cc = v cc max 20 40 ma i cc4 v cc standby current ce#, reset# = vcc 0.3 v, oe# = v ih , v cc = v cc max v il = vss + 0.3 v/-0.1v, 2.0 20 a i cc5 v cc reset current reset# = vss 0.3v 2.0 20 a i cc6 automatic sleep mode v ih = vcc 0.3v v il = vss 0.3v 2.0 20 a wp#/acc pin 3 10 i acc acc accelerated program current ce# = v il, oe# = v ih, v cc = v ccmax, wp#/acc = v hh v cc pin 15 30 ma v il input low voltage -0.5 0.3 x v io v v ih input high voltage 0.7 x v io v io + 0.3 v v hh acceleration program voltage 8.5 9.5 v v ol output low voltage i ol = 100 a 0.15 x v io v v oh output high voltage cmos i oh = -100 a 0.85 x v io v v lko supply voltage (erase and program lock-out) 2.3 2.5 v
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 37 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 figure 11. test conditions table 16. test specifications test conditions -70 unit output load capacitance, c b l b 30 pf input rise and fall times 5 ns input pulse levels 0.0-3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 38 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 ac characteristics table 17. read-only operations characteristics parameter symbols speed jedec standard description test setup -70 unit t avav t rc read cycle time min 70 ns t avqv t acc address to output delay ce# = v il oe#= v il max 70 ns t elqv t ce chip enable to output delay oe#= v il max 70 ns t pacc page access time max 25 ns t glqv t oe output enable to output delay max 25 ns t ehqz t df chip enable to output high z max 20 ns t ghqz t df output enable to output high z max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns read min 0 ns t oeh output enable hold time toggle and data # polling min 10 ns notes: 1. high z is not 100% tested. 2. for - 70 vcc = 2.7v ? 3.6v output load : 1 ttl gate and 30pf input rise and fall times: 5ns input rise levels: 0.0 v to 3.0 v timing measurement reference level, input and output: 1.5 v figure 12. ac waveforms for read operations addresses ce# oe# we# outputs reset# ry / by # t b acc 0v high z output valid t b ce b t b oh t b df t b oeh b high z t b oe b t b rc b addresses stable
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 39 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 figure 13. page read operation timings note: addresses are a2:a-1 for byte mode.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 40 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 ac characteristics table 18. hardware reset (reset#) speed paramete r std description test setup -70 unit t rp1 reset# pulse width (during embedded algorithms) min 10 us t rp2 reset# pulse width (not during embedded algorithms) min 500 ns t rh reset# high time before read min 50 ns t rb1 ry/by# recovery time ( to ce#, oe# go low) min 0 ns t rb2 ry/by# recovery time ( to we# go low) min 50 ns t ready1 reset# pin low (during embedded algorithms) to read or write max 20 us t ready2 reset# pin low (not during embedded algorithms) to read or write max 500 ns figure 14. ac waveforms for reset# reset# timings ce#, oe# we# ry/by# reset# t rp1 t ready1 t rb2 t rb1 reset timing during embedded algorithms reset# ry/by# ce#, oe# t ready2 t rh t rp2 reset timing not during embedded algorithms
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 41 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 ac characteristics table 19. word / byte configuration (byte#) speed std parameter description test setup -70 unit t bcs byte# to ce# switching setup time min 0 ns t cbh ce# to byte# switching hold time min 0 ns t rbh ry/by# to byte# switching hold time min 0 ns figure 15. ac waveforms for byte# byte# timings for read operations byte #timings for write operations note: switching byte# pin not allowed during embedded operations ce# we# t b cs b y te# t rbh ry/by# t c bh t b cs ce# oe# byte#
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 42 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 ac characteristics table 20. write (erase/program) operations parameter symbols speed jedec standard description -70 unit t avav t wc write cycle time min 70 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 45 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns read min 0 ns t oeh output enable hold time toggle and data# polling min 10 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setuptime min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 20 ns write buffer program operation (note 2, 3) typ 160 s typ 8 s t whwh1 t whwh1 programming operation (word and byte mode) max 200 s typ 0.1 s sector erase operation max 2 s t whwh2 t whwh2 chip erase operation typ 30 s t vhh v hh rise and fall time min 250 ns t vcs vcc setup time min 50 s t b busy we# high to ry/by# low max 70 ns t rb recovery time from ry/by# min 0 ns notes: 1. not 100% tested. 2. see table.22 erase and programming performance for more information. 3. for 1~32 words bytes programmed.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 43 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 ac characteristics table 21. write (erase/program) operations alternate ce# controlled writes parameter symbols speed jedec standard description -70 unit t avav t wc write cycle time min 70 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 30 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to ce# low) min 0 ns t wlel t ws we# setuptime min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp write pulse width min 35 ns t ehel t cph write pulse width high min 20 ns write buffer program operation (note 2, 3) typ 160 s typ 8 s t whwh1 t whwh1 programming operation (word and byte mode) max 200 s typ 0.1 s t whwh2 t whwh2 sector erase operation max 2 s notes: 1. not 100% tested. 2. see table.22 erase and programming performance for more information. 3. for 1~32 words bytes programmed.
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 44 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 ac characteristics figure 16. ac waveforms for chip /sector erase operations timings notes: 1. sa=sector address (for sector erase) , va=valid address for reading status, d out =true data at read address. 2. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. 10 for chip erase t dh t d s 0x55 0x30 status d ou t t whwh2 v cc a ddresses ce# oe# we# data ry/by# t c h t g hw l t c s t wph t wp t b us y t rb t v cs erase command sequence (last 2 cycles) read status data (last two cycles) t ah t w c 0x2aa s a v a v a t a s 0x555 for chip erase
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 45 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 figure 17. program operation timings notes: 1. pa=program address, pd=program data, d out is the true data at the program address. 2. v cc shown in order to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. t vcs t whwh1 t busy t ds t dh d out status pd oxa0 t rb t ah t as t wc 0x555 pa pa pa program command sequence (last 2 cycles) program command sequence (last 2 cycles) t ghwl data ry/by# v cc we# addresses ce# oe# t ch t wph t cs t wp
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 46 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 figure 18. ac waveforms for /data polling during embedded algorithm operations notes: 1. va=valid address for reading data# polling status data 2. this diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cy cle. figure 19. ac waveforms for toggle bit during embedded algorithm operations t b u s y t o eh t df t o e t c e t c h t a cc t r c v a v a v a t o h valid data true com p lement comple -ment status data status data true valid data ce# addresses oe# we# dq[7] dq[6:0] ry/by# t c e t o e t c h valid data valid status valid status valid status (first read) (second read) (stops toggling) a ddresses ce# oe# we# dq6, dq2 ry/by# t r c t a cc v a v a v a v a t o eh t df t o h t b usy
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 47 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 figure 20. alternate ce# controlled write operation timings notes: pa = address of the memory location to be programmed. pd = data to be programmed at byte address. va = valid address for reading program or erase status d out = array data read at va shown above are the last two cycles of the program or erase command sequence and the last status read cycle reset# shown to illustrate t rh measurement references. it cannot occur as shown during a valid command sequence. figure 21. dq2 vs. dq6 we# dq6 dq2 enter embedded erase erase suspend enter erase suspend program erase resume erase enter suspend read enter suspend program erase erase complete erase suspend read t rh t wh t ghel t cp pd for program 0x30 for sector erase 0x10 for chip erase 0xa0 for program 0x55 for erase d out status t busy t ds t dh t cph t ws t whwh1 / t whwh2 addresses we# oe# ce# data ry/by reset# t ah t as t wc va pa for program sa for sector erase 0x555 for chip erase 0x555 for program 0x2aa for erase
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 48 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 table 22. erase and programming performance limits parameter typ max unit comments sector erase time 0.1 2 sec chip erase time 30 120 sec excludes 00h programming prior to erasure byte programming time 8 200 s word programming time 8 200 s byte 134.4 403.2 chip programming time word 67.2 201.6 sec total write buffer time 160 acc total write buffer time 60 s excludes system level overhead erase/program endurance 100k cycles minimum 100k cycles notes: 1. typical program and erase times assume the follo wing conditions: room tem perature, 3v and checkboard pattern programmed. 2. maximum program and erase times assume the following conditions: worst case vcc, 90 c and 100,000 cycles. table 23. 56-pin tsop pin capacitance @ 25c, 1.0mhz parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf note: test conditions are temperature = 25c and f = 1.0 mhz. table 24. data retention parameter description test conditions min unit 150c 10 years data retention time 125c 20 years
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 49 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 absolute maximum ratings parameter value unit storage temperature -65 to +150 c plastic packages -65 to +125 c ambient temperature with power applied -55 to +125 c output short circuit current p 1 p 200 ma oe#, reset# p p and wp#/acc p 2 p -0.5 to + 9.5 v all other pins p 3 p -0.5 to vcc+0.5 v voltage with respect to ground vcc -0.5 to + 4.0 v notes: 1. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. 2. minimum dc input voltage on oe#, reset# and wp#/acc pins is ?0.5v. during voltage transitions, oe#, reset# and wp#/acc pins may undershoot v b ss b to ?1.0v for periods of up to 50ns and to ?2.0v for periods of up to 20ns. see figure below. maximum dc input voltage on oe#, and reset# is 8.5v wh ich may overshoot to 9.5v for periods up to 20ns. 3. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, inputs may undershoot v b ss b to ?1.0v for periods of up to 50ns and to ?2.0 v for periods of up to 20ns. see figure below. maximum dc voltage on output and i/o pins is v b cc b + 0.5 v. during voltage transitions, outputs may overshoot to v b cc b + 1.5 v for periods up to 20ns. see figure below. 4. stresses above the values so mentioned above may cause permanent damage to the device. these values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. recommended operating ranges p 1 p parameter value unit ambient operating temperature industrial devices -40 to 85 c operating supply voltage vcc full voltage range: 2.7 to 3.6v v 1. recommended operating ranges define those limits between which the functionality of the device is guaranteed. vcc +1.5v maximum negative overshoot maximum positive overshoot waveform waveform
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 50 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 figure 22. 56l tsop 14mm x 20mm package outline min. nor max a - - - - - - 1.20 a1 0.05 - - - 0.15 a2 0.95 1.00 1.05 d - - - 20.00 - - - d1 - - - 18.40 - - - e - - - 14.00 - - - e - - - 0.50 - - - b 0.170.220.27 l 0.5 0.60 0.70 r0.080.150.20 0 0 3 0 5 0 note : 1. coplanarit y : 0.1 mm symbol dimension in mm
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 51 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 figure 23. 64 ball ball grid array (fbga), 11 x13 mm, pitch 1mm package outline min. nor max a - - - - - - 1.40 a1 0.40 0.50 0.60 a2 0.60 0.66 0.76 d 12.90 13.00 13.10 e 10.90 11.00 11.10 d1 - - - 7.00 - - - e1 - - - 7.00 - - - e - - - 1.00 - - - b 0.50 0.60 0.70 dimension in mm symbol
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 52 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 purpose eon silicon solution inc. (hereinafter called ?eon?) is going to provide its products? top marking on ics with < cfeon > from january 1st, 2009, and without any change of the part number and the compositions of the ics. eon is still keeping the promise of quality for all the products with the same as that of eon delivered before. please be advised with the change and appreciate your kindly cooperation and fully support eon?s product family. eon products? top marking cfeon top marking example: for more information please contact your local sales office for additional information about eon memory solutions. cfeon part number: xxxx-xxx lot number: xxxxx date code: xxxxx
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 53 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 ordering information en29gl128 h - 70 z i p packaging content p = rohs compliant temperature range i = industrial (-40 c to +85 c) package z = 56-pin tsop ba = 64-ball ball grid array (bga) 1.0mm pitch, 11mm x 13mm package speed 70 = 70ns sector for write protect (wp#/acc=l) h = highest address sector protected l = lowest address sector protected base part number en = eon silicon solution inc. 29gl = flash, 3v page mode flash memory 128 =128 megabit (16m x 8 / 8m x 16)
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.c om or modifications due to changes in technical specifications. 54 en29gl128h/l rev. k, issue date: 2010 / 05 / 11 revisions list revision no description date a preliminary 2009/01/23 b 1.add sector for write protect se lection in ordering information 2.modify ppb sector group in table 7 and figure 7. 3. modify sector erase descirption and figure 6. 2009/02/18 c 1. add internal pull-up description for wp# pin in table1 on page 4 2. add wp#/acc, vio pin in figure3 on page 4 3. modify toe from 30ns to 25ns in table 17 on page 40 and page 5 4. add secured silicon sector entry/exit command in table13 5. modify typo from sector erase suspend to erase/program suspend, from sector erase resume to erase/program resume in table13 6. modify package code for 56-pin tsop from t to z in ordering information on page 54 7. del table 22 and figure 20 temporary sector unprotect timing table and diagram and figure 21.sector protect/unprotect timing diagram 8. modify erase/program perform ance in table 20, 21 and 22. chip erase time from 32 ? 30sec typ and 280 ? 120sec max. add acc and total write buffer time spec 9. correct typo from byte to word on page 7 10. del t ceh in table 17 11. modify dc characteristics in table 15 vhh from 10.5~11.5v to 8.5~9.5v icc1 5mhz 9 ? 15ma typ, 10mhz 16 ? 25ma typ icc4, icc5 and icc6 1 ? 1.5ua typ, 5 ? 10ua max add iio2 and iaccspec 12. del apply vid on address pin a9 to access autoselect codes function. ( remove table 5 and modify description autoselect section for using high voltage to get autoselect codes ) 13. modify a9 spec from 9.5v to vcc+0.5v in absolute maximum ratings 14. modify cfi 4ah, 4fh descripti on and data of 4fh in table 12 2009/05/12 d 1. modify naming for dq0 otp lock bit to secured silicon sector protection bit on page 25 2. modify table.8 secured silicon sector address range 000000h- 000007h from determined by customer to reserve for factory 3. add note ?the addre ss 0h~7h in secured silicon sector is reserved for factory? on page 31 2009/06/19 e update figure 23. 64 ball fortified ball grid array (fbga), 11 x13 mm, pitch 1mm package outline on page 52 2009/07/01 f 1. modify from sector 0 to all sectors in note 1 of table 6 and note 2, 3 and note 9 of ppb section on page 25. 2. add ?user only can use dq6 and ry/by# pin to detect programming status? in note 10 on page26. 2009/07/14 g change the package code of 64-ball bga on page 53. 2009/07/22 h correct typo in table 20, ? t b busy ? from min. to max on page 42. 2009/10/01 i add a note "when sector sa0 is susp ended, if system enters secured sector mode,." on page 29. 2009/11/02 j add write buffer byte mode command and note that maximum value is 31 for word and byte mode in page 34 2010/02/10 k 1. update table 15. dc characteristics on page 36. (1) icc3 from 30ma to 40ma. (max.) (2) icc4, icc5, icc6 from 1.5/10ua to 2.0/20ua (typ./max.) 2010/05/11

▲Up To Search▲

Price & Availability of EN29GL128HH70BAIP

	To Download EN29GL128HH70BAIP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .